The IC industry has developed for four decades from the birth of the first semiconductor device in 1960. With the progressing of the semiconductor manufacturing technology, the number of devices on a chip increases explosively. A semiconductor chip has in general millions of devices or more devices with present ULSI (ultra large scale integration) technology. For fabricating such a densely packed circuits, every device has to be manufactured with smaller size without damaging the operational characteristics. New challenges accompanying with smaller feature size like latch up problem and yield rate of fabrication must be considered at the same time.
With the present and future developments of semiconductor manufacturing into sub-micrometer and smaller feature size, the chip size is getting bigger and the size of the devices is getting smaller. The characteristics of active region and the operation of the device are easily influenced by neighboring devices under narrower device to device isolation. The problem is enhanced especially for devices located at the edge region of an operational array. Thus the yield of the fabricating process can be greatly reduced with lower uniformity at the array edge under the increased integrity of the integrated circuits. The latch up problem of the operational devices are also enhanced. For integrated circuits array like memory cell array or more specifically ROM (read only memory) array, the devices must be carefully protected from the latch up problem to ensure the functionality of the cell or the circuits.
In conventional integrated circuits array, the addition of a dummy cell array is presented to surround an active array of functional devices. As shown in FIG. 1, a schematic figure of an integrated circuits array 10 is illustrated. The active array 12 contains a plurality of functional devices for performing the operation of the circuits. A dummy cell array 14 with non-functional devices are formed around the active array 12. The low yield from the low uniformity problem especially at the edge of the active array 12 can be relieved by the dummy cell array 14.
For protecting active array 10 like memory array or ROM array from latch up problem, an additional guard ring 16 is employed. In general, the guard ring 16 is formed outside the dummy cell array 14 for latch up protection. The guard ring 16 in conventional devices contains a plurality of substrate or well contacts for forming a guard ring circulating the active array 12 with dummy cell array 14 in-between.
By applying the dummy cell array 14 and the guard ring 16 on the outer edge of the active array 12, the yield problem and the latch up problem can be reduced. However, all the devices in the dummy cell array 14 and the guard ring 16 are non-functional devices. A great number of non-functional devices are needed for each integrated circuits array 10 and thus the area left on a chip for functional devices in the active array 12 is significantly reduced. Thus the packing density of the IC chips is reduced and the cost for the circuits is hard to cut down.